1. Field of the Invention
The present invention relates to a method of forming element isolating region in a semiconductor device.
2. Description of the Background Art
Recently, as the degree of integration of semiconductor devices such as a dynamic random access memory (DRAM) has been increased, an application of a trench isolation method which allows element isolation in smaller region as compared with the conventional LOCOS has been proposed as a method of forming element isolation.
An example in which trench isolation method is employed for isolating elements at a memory cell portion of a dynamic random access memory will be described with reference to FIGS. 19 to 24.
First, referring to FIG. 19, a resist layer 2 is formed on a main surface of a semiconductor substrate 1 of a silicon substrate having a first conductivity type (for example, P type). An opening a is formed in resist layer 2. The opening 2a of resist layer 2 is formed at a position on which an element isolating region is formed on the semiconductor substrate 1 surrounding the element forming region of semiconductor substrate 1.
Using resist layer 2 having the opening 2a as a mask, the main surface of semiconductor substrate 1 exposed through opening 2a is etched by conventional etching technique, and a trench 3 is formed at the element isolation forming region of semiconductor substrate 1.
Then, referring to FIG. 20, using resist 2 having opening 2a formed as a mask, an impurity of a first conductivity type is introduced by ion implantation and Oblique ion implantation, thus an impurity layer 4 (serving as a channel stopper) for isolating elements is formed on the bottom surface and side surfaces of trench 3 formed in semiconductor substrate 1.
Then, referring to FIG. 21, resist layer 2 is removed, an insulating layer is formed by the CVD method on the main surface and in the trench 3 of semiconductor substrate 1, and thereafter the insulating layer is etched back so as to remove the insulating layer on the main surface of semiconductor substrate 1 entirely, whereby a buried insulating layer 5 is formed only in trench 3.
By the trench 3, impurity layer 4 and buried insulating layer 5 formed in this manner, an element isolation region surrounding the element forming region of semiconductor substrate 1 is provided.
Referring to FIG. 22, on the main surface of semiconductor substrate 1 and on the buried insulating layer 5, a gate insulating film 6 of silicon oxide (SiO.sub.2) is formed, a polycrystalline silicon layer is formed on gate insulating film 6, the polycrystalline silicon layer is etched and thus a plurality of word lines 7 each having a gate electrode 7a are formed parallel to each other.
Then, using gate electrode 7 as a part of a mask, an impurity of a second conductivity type (for example, N type) is introduced by ion implantation in self-aligned manner, whereby a pair of source/drain regions 8 and 9 is formed.
Gate electrode 7a and a pair of source/drain regions 8 and 9 constitute a switching transistor of a memory cell. One of the source/drain regions 8, in this example, the source/drain region formed between adjacent gate electrodes 7a formed on the element forming region of the semiconductor substrate 1 serves as source/drain region of two switching transistors, and is connected to a bit line, which will be described later. The other one of the source/drain regions 9, in this example the source/drain region in contact with impurity layer 4, is connected to a storage node (which will be described later), which is one of the electrodes constituting a capacitive element of the memory cell.
Referring to FIG. 23, on the main surface of semiconductor substrate 1 and on word lines 7, an insulating layer 10 is formed by the CVD method, and a contact hole 10a is formed at a position of insulating layer 10 where one of the source/drain regions 8 is positioned. On insulating layer 10, a bit line 11 which is connected to one of the source/drain regions 8 through contact hole 10a is formed.
Then, referring to FIG. 24, an insulating layer 12 is formed by the CVD method on insulating layer 10 and bit line 11, and contact holes 12a and 10b are formed at positions of insulating layer 12 and 10 where the other one of the source/drain regions 9 is positioned. On insulating layer 11, a storage node 13 which is connected to the other one of the source/drain regions 9 through contact holes 12a and 10b is formed.
A dielectric film 14 is formed on storage node 13, and a cell plate 15 is formed on the entire surface of dielectric film 14. Storage node 13, dielectric film 14 and cell plate 15 formed in this manner constitute a capacitive element of the memory cell.
Thereafter, an insulating layer 16 is formed on cell plate 15 by the CVD method, and an interconnection layer 17 of aluminum opposing to word line 7 and electrically connected to the opposing word line 7 at a prescribed position is formed on insulating layer 16.
Thereafter, passivation film and the like are formed, thus completing a dynamic random access memory.
However, in the dynamic random access memory manufactured in this manner, impurity layer 4 in the element isolating structure involves crystal defects caused by ion implantation. When impurity layer 4 including crystal defects is in contact with the source/drain regions 8 and 9 of the switching transistor, leak current from source/drain regions 8 and 9 through impurity layer increases, resulting in degraded device characteristics such as degraded retention. Further, when more minute element isolating region is to be formed, the aspect ratio (ratio of the length and width of the total of opening 2a of insulating layer 2 and trench 3) at the time of ion implantation for forming impurity layer 4 is increased, and therefore control in forming impurity layer 4 becomes difficult.